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Kai Klaas
08/02/06 22:47
Read: 3102 times

#121603 - Thanks! I recall it here:"80C52 port circuitry"
Responding to: Erik Malund's previous message
Joe said:
For new commers the hardware reference manuals on 80c51 Quasi-Bidirectional I/O ports.. can be a little daunting.
Does anyone have something they found on the web that simply descibe the I/O ports other than the mfg hardware references doc's?

80C52's port circuitry is very simple to understand, if you have a look at this issue from the right point-of-view:

In order to obtain highest versatility inventor of 80C52 has designed the ports of micro to provide both, input and output capability. Have you already thought about how a port circuitry could look like serving as input AND ouptut?

Have a look at the following scheme, for instance:

You see an ouput stage provided by an nFET and a pull-up resistor "R". When the gate is high, the nFET is turned-on, the output is low and the port pin emits low level. But if the gate is low, on the other hand, the nFET is turned-off, the output is pulled high by the pull-up resistor "R" and the port pin emits high level.
The gate is driven by an inverter to provide true "output data", means if data at "output data" terminal is high for instance, then port pin emits high level too.

Also connected to the port pin is the input of a CMOS-gate, which buffers the level at port pin. So, at the output of this buffer "input data" can be read.

How will this port circuitry work as input and output?

Well, the output is always emitting the data being present at "output data" terminal. So, by applying the according data to "output data" terminal the port circuitry will work as an output.

To work as input, means to make it possible for the micro to read the data being driven into the port pin by an external device, just make the nFET being turned-off. Then, only the pull-up resistor "R" is present, which (if not too small) easily allows the external device to drive the port pin high or low.

So, to work as an input "output data" terminal must be high! But keep in mind, that the output still works as an output, as it emits high level. It's not, that you can switch between input and output mode or anything like that. You only allow the micro to read the input buffer, by turning-off the nFET.

Of course, care must be taken, that the nFET isn't turned-on while the external device tries to drive the port pin high!
No destruction occurs, when the external driver also consists of such a port circuitry, like shown here:

When the left micro wants to recieve data from the right one, for instance, then it drives its "output data" terminal high and reads the "input data" buffer.

What are the disadvantages of this port circuitry?

In order to produce steep edges when toggling, the port line must be driven by a low impedant circuitry. This is fullfilled for high to low egdes, when the nFET is turned-on. But not for low to high edges, when the nFET is turned-off. Then, only the rather high impedant pull-up resistor will charge the unavoidable stray capacitance sitting on port line, resulting in smooth egdes and slowing down the communication rate. Then, a very low pull-up resistor "R" would be helpful, or a push-pull output stage containing a nFET plus pFET, like it's used in 74HCMOS chips.

Not only because of obtaining steep edges a small pull-up resistor "R" is wished, but also to suppress the injecting of noise via unavoidable stray capacitance!

On the other hand, if the pull-up resistor "R" is very small, then an enormous supply current is drawn whenever the port pin is pulled-down! Keep in mind that the 80C52 has 4 ports in total, each containing 8 port lines, yielding 32 port lines in total. An unsuited chosen pull-up can result in huge supply currents!!

The inventors of 80C52 therefore used a trick, to allow steep edges, to guarantee sufficient noise immunity and to keep the supply currents adequately small, at the same time. They modified the pull-up and provided that the strength of pull-up and by this the additional supply current can change accordingly to the different modes of operation and the different needs! By this, it's also guaranteed, that no destruction occurs, when two such port circuitries simultaneously try to drive the same port line.

Have a look at the following simplified schematic, which shows the actual port circuitry of 80C52:

You again see the nFET driven by an inverter and the input data buffer, but here splitted into two inverters. Instead of pull-up resistor "R" you see three pFETs:

pFET1 provides a strong pull-up. In combination with the nFET it works like a push-pull output stage of a 74HCMOS chip, allowing the fabrication of steep egdes, not only for high to low transitions but also for low to high transitions. But pFET1 is turned-on for only two oscillator periods of micro! This is enough to fully charge or discharge the stray capacitance of port line, but not enough to destroy pFET1, when the port pin is pulled-down to ground by an external device. pFET1 is designed to withstand these brief shorts, if any.
So, whenever a 1s is going to be written into the according SFR (port latch), pFET1 is turned-on for two oscillator periods.

pFET2 is turned-on, whenever 1s is written into the according SFR. It's permanently on, not only for two oscillator periods like pFET1. pFET2 serves as a very weak pull-up. Although not being a resistor but more a current source, pFET2 roughly behaves like a resistor of about 100...200kOhm.

pFET3 is a weak pull-up, roughly behaving like a resistor of about 10...20kOhm. pFET3 is active, whenever the port pin is at high level.

Take care: The gate of pFET3 is not driven by the SFR content, but by the first inverter connected to the output itself, forming a positive feedback: pFET3 is turned-on, when port pin is at high level, and is turned-off, on the other hand, when port pin is at low level. Trip point is at about 2V.

At the first sight this seems to be very strange. Why not connecting the gate of pFET3 to the gate of nFET like pFET2?
The reason is simple: I stated earlier, that a rather strong pull-up should be present to keep the port line immune against injected noise. But this would cause rather big additional supply current, when the port pin is pulled-down by an external device. On the other hand, when the port pin is at low level, because pulled-down by an external load, we can assume a sufficient low source impedance of the external device and we should have a very weak pull-up to keep the additional supply current minimal. So what we need is a scheme which provides a stronger pull-up, when port pin is at high level and a weaker pull-up, when the port pin is at low level. And just this is accomplished by the gate control circuitry arround pFET3! By other words: The potential at port pin itself determines whether pFET3 is turned-on or -off, whether a stronger pull-up (pFET2 + pFET3) or a weaker (only pFET2) is active!

Tutorials often mention, that the gate control circuitry of pFET3 forms a latch. But this only means that a positive feedback is fabricated to allow to control the gate of pFET3 depending on potential at port pin. This does NOT mean, that the inverter is latching the input data anyhow! There's no such input data latch. You have to store the input data to a suited memory location by the help of a move instruction, if you want to latch it.


List of 12 messages in thread
80c51 Quasi-Bidirectional I/O ports      Joe Gold      08/02/06 11:20      
   Like this ?      Steve M. Taylor      08/02/06 11:25      
      I agree the nomclature could be better      Jez Smith      08/02/06 14:16      
   Kai?      Erik Malund      08/02/06 11:25      
      Thanks! I recall it here:"80C52 port circuitry"      Kai Klaas      08/02/06 22:47      
         8051 I/O Port      Joe Gold      08/03/06 07:51      
            Diplomacy      Steve M. Taylor      08/03/06 14:12      
   It's the nomenclature that's the problem      Richard Erlacher      08/02/06 13:38      
      why not call a spade a spade      Erik Malund      08/02/06 15:04      
   the value of a newbie's question      Jan Waclawek      08/02/06 15:36      
   Spade a spade Jokes      Charles Bannister      08/02/06 17:07      
      Unwarranted        Jerson Fernandes      08/02/06 23:54      

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