Was all hardware designed long-time ago, or is your banking pin a recent hardware change?

As already noted, you get a number of problems if you let the same processor pin switch both data and code banks. It cuts off a lot of your sw design options. You either must access the banked variables from a common code bank, or use helper functions for the switching. And you do not want any ISR to touch anything banked.

This is a big reason why you always have to look ahead when designing the hardware. And even if your initial software don't need all features of a hardware platform, you have to write test applications that validates all parts of the design - this includes possible interference between code bank switching and data bank switching, trying to maximize current consumption, trying maximum signal frequencies on all relevant signal lines, submitting the board to noise levels way above the expected installation environment etc.