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Maarten Brock
09/29/09 15:58
Read: 197 times
Tilburg
The Netherlands


 		 #169271 - prototype visible to main
Responding to: Csmg Sarma's previous message
Sarma,

Is the ISR implementation or its prototype visible to main? As documented SDCC needs this to generate the interrupt vector.

Maarten

List of 13 messages in thread
TopicAuthorDate
Timer 2 Interrupt Enable?      CSMG Sarma      09/29/09 08:41      
   do you actually clock the T2EX?      Erik Malund      09/29/09 10:23      
      Yes I am      CSMG Sarma      09/30/09 01:13      
   prototype visible to main      Maarten Brock      09/29/09 15:58      
      Some Differences Found in Documentation      CSMG Sarma      09/30/09 01:26      
         who know the most about NXP chips ?        Erik Malund      09/30/09 06:44      
            Can't Get Your Point      CSMG SARMA      09/30/09 07:12      
               YES      Erik Malund      09/30/09 09:26      
   One Problem Fixed      CSMG Sarma      09/30/09 04:49      
      wrong include        Maarten Brock      09/30/09 15:08      
         This was the Exact Problem      CSMG Sarma      09/30/09 23:47      
            re include files      Erik Malund      10/01/09 05:32      
   Please check .RST file      Mahesh Joshi      09/30/09 07:56      

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