There are some FPGA families which have onboard non-volatile configuration storage with "instant" configuration, meaning that as soon as power is stable the FPGA is configured. Actel's flash parts work this way. There are also OTP FPGAs (QuickLogic, Actel) which are also ready as soon as power is stable.

The real difference between a CPLD and an FPGA is that of resources. A CPLD macrocell has a much wider combinatorial logic resource in front of its (single) register than an FPGA's slice. An FPGA's slice may have one, two or even four registers and a simpler (3-, 4- or 6-input) combinatorial lookup table. FPGAs also have significantly greater routing resources than CPLDs, which is necessary if you need wide muxes and such.

Timing in a CPLD is simpler to analyze because the paths are simpler and delays fairly constant, but that's not really interesting any more since you do your FPGA design, set a clock period constraint, and let the tools have at it and they'll tell you if you win or not.

-a