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Richard Erlacher
11/29/11 15:08
Read: 415 times
Denver, Co
USA


 
#184946 - This will continue until ...
Responding to: Michael Karas's previous message
I agree that as long as manufacturers don't provide better reset circuits than the old classic, we'll see nothing better from them.

The problem lies in the poorly specified relationship between rise and fall time of Vcc, the oscillator startup time, and the MCU behavior during the interval between oscillator startup and proper Vcc level while the RESET voltage is still out of specified limits.

From what I've gathered, one specified reset characteristic is that the MCU requires a period of 24 oscillator cycles to "get its self together" during active RESET, so that defines a minimal reset pulse width. I've seen no comparable characterization that's applicable to the one-clockers, two-clockers, etc.

Flash memories, NVRAM, etc, that are expected to be nonvolatile don't seem to have compatible spec's with the RESET voltage and Vcc levels specified for some 805x's (I haven't seen all the spec's). Maxim/Dallas, just for example, specifies the write-inhibit levels for their NVRAM differently than they specify them for their MCU's, and also for their supervisor chips. This can lead to a lot of confusion, and makes it hard to guess which of their thresholds should be tweaked to make these devices play together.

I've observed runaway write behaviors on Maxim/Dallas, and other 805x's during active RESET during the decay of Vcc. One of these days, when I am able to locate the fixture in which I observed that (I moved a couple of years ago, and not everything has surfaced yet.) and I'll try to get a good "picture" of it doing exactly that.

If there are good spec's for the relationships between Vcc rise/fall, oscillator startup, and reset width, particularly for some of the newer, non-12-clockers, I'd be very interested.

RE




List of 25 messages in thread
TopicAuthorDate
P89V51RD2 And Flash Magic      Arif Deshmukh      11/26/11 18:48      
   please suggest      Andy Neil      11/26/11 23:27      
   reset button      Jan Waclawek      11/27/11 01:52      
      Reset Button      Arif Deshmukh      11/27/11 09:26      
         reset circuit      Jan Waclawek      11/27/11 13:04      
            That's the fundamental flaw with RC resets!      Andy Neil      11/28/11 14:40      
   Use a MAX700      Matthias Arndt      11/29/11 00:15      
      Rest supervisor        Steve M. Taylor      11/29/11 03:56      
         How Many Times      Michael Karas      11/29/11 05:03      
            This will continue until ...      Richard Erlacher      11/29/11 15:08      
               Power dip      Per Westermark      11/30/11 05:01      
                  real, but worse if flash      Erik Malund      11/30/11 07:17      
                  note, that here the main problem is NOT power related...      Jan Waclawek      11/30/11 07:17      
                     Yes      Per Westermark      11/30/11 07:42      
                        the ultimate joke      Erik Malund      11/30/11 08:20      
                           SiLabs watchdog      Andy Peters      11/30/11 09:25      
                              clarification      Erik Malund      11/30/11 09:43      
                                 Beware flash erase time      Maarten Brock      12/01/11 10:03      
                           brownout detection      Maarten Brock      12/01/11 10:07      
                              well,      Erik Malund      12/01/11 10:09      
                  It's not the spec's ... it's the lack of them.      Richard Erlacher      11/30/11 12:43      
   Reset Chip?      Arif Deshmukh      11/29/11 21:04      
      Why Ask???      Michael Karas      11/29/11 21:33      
         Thanks      Arif Deshmukh      11/30/11 00:29      
            a plethora of possible chips      Erik Malund      11/30/11 07:19      

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