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Erik Malund
12/14/11 06:22
Modified:
  12/14/11 06:24

Read: 718 times
Mt Airy, Nc
USA


 
#185085 - Ok, a SILabs cache lesson
Responding to: Jan Waclawek's previous message
Now this means, that if there is a cache miss, the instruction may take 4 cycles more to fetch the word containing the target of the jump. That happens only when the jump is taken with the conditionals, so I should write say 3/4+4 for JB, correct?

My problem is, that the datasheet mentions also less-than-four-cycle cache-miss penalties. How comes? I couldn't really find the explanation in the datasheet, and did not dig deeper back then (nor now).


by my best understanding I'd like to be corrected if I'm wrong

the below is if you do not use cache lock

the main flash is 4 bytes (24-bit) wide and takes 4 cycles to load to the cache.

so, if you have a jump to some different place it takes 4 cycles to get to the first byte.

if that is the first byte of the 4 loaded all is well.

if iis the 2nd or 3rd - figure it out by the below

if it is the last byte of the 4 there will be a 3 clcok delay to fetch the next word to the cache.

thus if you have VERY critical rouitine with a frequent jump do one of two

a) locate it at a boundary if 4 and lock the first flash word
b) lock the first two cach words.

in other words, jumps CAN match the stated no of cycles, but do not necessarily do so

Erik



List of 19 messages in thread
TopicAuthorDate
'51 derivatives cycle comparison table updated      Jan Waclawek      12/11/11 15:29      
   above about 40 Mhz devices may need extra cycles      Frieder Ferlemann      12/12/11 15:11      
      silabs with cache      Jan Waclawek      12/13/11 15:27      
         Ok, a SILabs cache lesson      Erik Malund      12/14/11 06:22      
            Bytes      Michael Karas      12/14/11 11:08      
               ecc?      Per Westermark      12/14/11 12:44      
               not the cookies      Erik Malund      12/15/11 07:17      
                  Washed?      Michael Karas      12/15/11 09:55      
                     am I as has happened before ...      Erik Malund      12/15/11 10:10      
                        Is that how it's spelled?      Richard Erlacher      12/15/11 12:52      
                     re: Washed?      Andy Peters      12/16/11 09:35      
            jump cache miss penalty      Jan Waclawek      12/15/11 00:35      
               clarifications      Erik Malund      12/15/11 07:33      
               no cache for 50MHz      Maarten Brock      12/15/11 16:01      
                  surely not all      Jan Waclawek      12/16/11 07:13      
                     you missed a word      Erik Malund      12/16/11 07:18      
   more update      Jan Waclawek      01/02/12 15:21      
      Table suggestions      Jim Granville      02/14/12 23:52      
      Updated MC51 supports Cycle Define      Jim Granville      04/26/12 16:17      

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