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Erik Malund
12/15/11 07:33
Read: 684 times
Mt Airy, Nc

#185101 - clarifications
Responding to: Jan Waclawek's previous message
I would expect exactly this behaviour only if all of the instructions at the jump target would be single-world single-cycle (NOP-like). As most of the instructions (even the single-word) take more than that, I would expect slightly less penalty in average.
the length of the first instruction doe not matter, the next one needs to be cached.

So, in effect, that all means, that a jump to a non-cached position may result in delay of 4-7 cycles (the 1-3 extra cycles would "happen" at a different instruction and under the circumstances outlined above, but I think it is an adequate description for the purpose of a worst-case description for the table). A jump into a non-cached position may result in delay of 1-3 cycles, if the next word is not cached yet. Correct?
if the next instruction is cache-locked, there may be a delay, see above


List of 19 messages in thread
'51 derivatives cycle comparison table updated      Jan Waclawek      12/11/11 15:29      
   above about 40 Mhz devices may need extra cycles      Frieder Ferlemann      12/12/11 15:11      
      silabs with cache      Jan Waclawek      12/13/11 15:27      
         Ok, a SILabs cache lesson      Erik Malund      12/14/11 06:22      
            Bytes      Michael Karas      12/14/11 11:08      
               ecc?      Per Westermark      12/14/11 12:44      
               not the cookies      Erik Malund      12/15/11 07:17      
                  Washed?      Michael Karas      12/15/11 09:55      
                     am I as has happened before ...      Erik Malund      12/15/11 10:10      
                        Is that how it's spelled?      Richard Erlacher      12/15/11 12:52      
                     re: Washed?      Andy Peters      12/16/11 09:35      
            jump cache miss penalty      Jan Waclawek      12/15/11 00:35      
               clarifications      Erik Malund      12/15/11 07:33      
               no cache for 50MHz      Maarten Brock      12/15/11 16:01      
                  surely not all      Jan Waclawek      12/16/11 07:13      
                     you missed a word      Erik Malund      12/16/11 07:18      
   more update      Jan Waclawek      01/02/12 15:21      
      Table suggestions      Jim Granville      02/14/12 23:52      
      Updated MC51 supports Cycle Define      Jim Granville      04/26/12 16:17      

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