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03/06/12 10:59
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#186451 - MCS-51 UART Question
Hello...I've been using the Atmel AT89S8253 uC for a couple of months now and let me just say the MCS-51 family is a VERY fun uC family to code and work with.

However, most of my applications use the on chip UART. I have a question regarding receive buffer overflow.

On PIC microcontrollers (which is what I started on), they have a 2 level deep FIFO receive buffer, and any read instruction that addresses the receive buffer clears the top level of the buffer and transfers the byte in the bottom buffer level to the top buffer level. You can have two bytes in the receive buffer while a third byte is shifting into the RSR. However, if upon receiving the stop bit of the 3rd byte the buffer has not yet been read, it sets a buffer overrun error and disables the UART from further receiving activity until the error condition is cleared.

I understand the 8051 only has a single level receive buffer that can have one byte waiting in the buffer while a second byte is shifting into the shift register. However, in the event that I do not read the buffer prior to the stop bit of the second byte being received, does it set an overrun error condition that I have to clear before I can receive data again like the PIC does? Or does it simply transfer the received byte from the RSR to the buffer, thereby overwriting the previously received byte?

List of 2 messages in thread
MCS-51 UART Question      Jon Wilder      03/06/12 10:59      
   derivative dependent      Erik Malund      03/06/12 11:34      

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