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Per Westermark
09/26/12 04:21
Read: 779 times
Sweden


 
#188459 - Setup and hold times?
Responding to: ???'s previous message
Maybe one side have incorrect hold times. So it removes the control signals (address, r/w signal, ...) too soon. The slower memory chip continued to hold the data available a number of ns longer. With a faster RAM, you might now sometimes or always read garbage because the RAM isn't driving the data lines anymore when the processor finally do latch the data.

List of 18 messages in thread
TopicAuthorDate
SRAM issues      Harry Leung      09/26/12 04:09      
   Setup and hold times?      Per Westermark      09/26/12 04:21      
      RAM issues      Harry Leung      09/26/12 06:13      
         Or narrow pulses ?      Jim Granville      09/26/12 19:46      
      Address setup time      Harry Leung      10/02/12 20:48      
   did you change the arbitration?      Erik Malund      09/26/12 07:18      
      Ram issues      Harry Leung      09/26/12 07:36      
   P0, P2 for memory only, or ...      Erik Malund      09/26/12 09:04      
      p0 and p2      Harry Leung      09/27/12 03:29      
         If you latch both P0 and P2, there will be stabile A15-A0      Richard Erlacher      09/27/12 11:24      
   Arbitration circuit      Oliver Sedlacek      09/26/12 10:08      
   It's a bit tricky synchronizing an 805x with 68k series      Richard Erlacher      09/26/12 15:51      
   you are using a latch, and not a flipflop, right?      Richard Erlacher      09/26/12 22:54      
      FF or latch      Harry Leung      09/27/12 03:30      
         It's a mistake I've seen a time or two ...       Richard Erlacher      09/27/12 11:19      
            time wasting      Stefan KAnev      09/27/12 13:24      
               no circuit diagram      Harry Leung      09/27/12 20:38      
                  You don't have to do that      Richard Erlacher      10/05/12 13:45      

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