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09/27/12 20:22
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#188477 - AT89C51RC vs. AT89C51RC2
Responding to: Erik Malund's previous message

Thanks for your reply.

It's not clear to me that this is the problem. Based on the AT89C51RC2 datasheet (unless I've misread it) it sounds as if the device comes up with the X2 bit(s) cleared, which would put it into 8XC51 operational mode. See below. Note: The X2/CPU Clock bit is in the CKCON0 reg and is s/w programmable. The HSB X2 bit has to be set at FLASH programming time (Hmmmm...since I'm using ext. FLASH at the moment, I wonder if that might be an issue?)

Maybe I'm missing something else here.



CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
mode) and to enable the individual peripherals�X2� bits. Programmed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.

This is the info about the HSB (mentioned in the X2/CPU Clock above).....

X2 Mode
Programmed to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed to force X1 mode, Standard Mode, after reset (Default).

List of 9 messages in thread
AT89C51RC vs. AT89C51RC2      Steph Ru      09/27/12 13:22      
   set the 12 clock bit      Erik Malund      09/27/12 14:10      
      AT89C51RC vs. AT89C51RC2      Steph Ru      09/27/12 20:22      
   AT89C51RC vs. AT89C51RC2...SOLVED      Steph Ru      09/27/12 21:27      
   AT89LP51RB2/RC2/IC2      Jim Granville      09/28/12 00:00      
      AT89LP51RB2/RC2/IC2      Steph Ru      09/28/12 16:02      
      if so      Erik Malund      09/28/12 20:30      
         Of course, consider all parts that fit      Jim Granville      09/29/12 00:02      
   you can get answer from one document      Zhao Donglin      09/29/12 03:01      

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