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Richard Erlacher
12/02/12 10:15
Read: 914 times
Denver, Co
USA


 
#188948 - Have you any basis for that rate?
Responding to: Kai Klaas's previous message
Kai,

I haven't run into much information about the MCU behavior during rise/fall time of Vcc. While I agree that there are many things going on during rise and fall of Vcc, there should, in fact, be nothing externally observable happening during Vcc rise and fall if RESET is asserted, aside from oscillator startup during Vcc rise. Nevertheless, I've observed external signals, as mentioned previously, during the decay of Vcc to levels below the specified minimum after external power is cut off. As I've never completed my investigation into this matter, I'm still persuaded that something needs to be done to inhibit internal processes during active RESET.

From what I've observed, there are two critical timespans, one during power-up, which is less critical, and one during Vcc decay during shutdown, when internal processes, including the flash-write supervoltage charge pump, may still be running.

All these problems are addressable, albeit not so inexpensively. I suspect that they may be manageable with a small CPLD, which probably won't cost more than the larger supervisors, but certainly will impact cost more than the 3-terminal types, particularly in a system with a small, low-cost MCU.

One of these days, soon, I hope, I'll get back to this matter. I've never set up a complete test environment for it, and just the setup will take a couple of weeks, I suppose. Design of the mechanism to control the respective timing of RESET and Vcc rise and fall will take considerable time and effort. Presently, I'm persuaded that a very short rise-time, but one long enough to allow reliable oscillator startup is essential, and that a very short cutoff of Vcc, down to very nearly 0 Volts, is essential to stop the processes that, under presently common circumstances, continue while Vcc is decaying, where supervisors do little other than to assert RESET once Vcc is below tolerable levels, is what is needed.

If you can provide a link to a datasheet or other document that specifies details of Vcc rise and fall, I would be very grateful.

RE

List of 33 messages in thread
TopicAuthorDate
C8051F231 experiences      Daniel Contarino      11/30/12 14:43      
   another solution      Erik Malund      11/30/12 15:11      
   The probabilities are low...      Daniel Contarino      11/30/12 18:34      
      think about what happens when you add a finger      Richard Erlacher      11/30/12 22:55      
         The point is ...      Daniel Contarino      12/01/12 03:08      
            Yes ... the underlying issue is the flash ...       Richard Erlacher      12/01/12 11:28      
               Out of my office, but...      Daniel Contarino      12/01/12 14:05      
                  Don't think in Vcc, ESD or hum...      Daniel Contarino      12/02/12 09:24      
   Apparently several C8051F2xx parts have the same pinout      Richard Erlacher      12/01/12 14:25      
   Characteristic for in system programmable flash micros...      Kai Klaas      12/01/12 18:25      
      All too true ... sadly ...       Richard Erlacher      12/01/12 20:13      
         Power-on slope rate...      Kai Klaas      12/02/12 05:31      
            Sorry, my post should be here, no up there...      Daniel Contarino      12/02/12 09:58      
            Have you any basis for that rate?      Richard Erlacher      12/02/12 10:15      
               Vdd ramp time      Maarten Brock      12/03/12 06:15      
               Some datasheets show numbers...      Kai Klaas      12/03/12 07:05      
                  Those aren't the "usual" 805x-core MCU's      Richard Erlacher      12/03/12 17:43      
                     There aren't many "usual" 8051-cores anymore...      Kai Klaas      12/03/12 18:13      
                        How dangerous power ups can be...      Kai Klaas      12/04/12 06:20      
                           I believe it      Richard Erlacher      12/04/12 08:59      
                              (dV/dt) examples      Jim Granville      12/04/12 13:14      
                                 They don't know it either...      Kai Klaas      12/04/12 18:49      
                                    dV/dT etc       Jim Granville      12/04/12 21:39      
                                       reset request...      Kai Klaas      12/05/12 06:21      
                                          That's what disturbs me greatly      Richard Erlacher      12/06/12 00:19      
                                             It IS disturbing!      Kai Klaas      12/06/12 08:02      
                                                Where this began ... at least for me ...       Richard Erlacher      12/06/12 09:43      
                                                   So, you took the hard road...      Kai Klaas      12/06/12 10:41      
                                                      We've all had that experience       Richard Erlacher      12/06/12 16:23      
   probable cause      Brent Wilson      02/04/13 20:32      
      Brent, this is very nice      Erik Malund      02/05/13 06:38      
         forum no longer down      Maarten Brock      02/05/13 07:33      
      Thank you!      Daniel Contarino      02/05/13 15:04      

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