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Suresh R
02/17/06 05:01
Read: 693 times

#110221 - Logic 1 to 0 transition
Responding to: Kai Klaas's previous message
Kai Klaas said:

We had agreed some weeks ago, that we shouldn't talk about 'modes'.
Say instead: "If port is emitting logic low state." Or: "If port output is logic low." Or something similar.


Suresh said:

Logical 1 to 0 Transition Current(ITL) (Ports 1,2,3) = -650 A when VIN = 2V, VCC = 5V 10%
HOw this should be taken care of while connecting the driver circuit to the port.

Kai Klaas said:

This means, that if you want to force a port pin, which was programmed as input by writing '1s' into according SFR, to logic low, that you must take care that source impedance is not too high. Here, less than 2V / 650A = ca. 3kOhm. Otherwise the potential at port pin will never fall down to less than 2V, which is needed to detect logic low state.

Let me take an example:
If i have connected a PNP to port1.x.
Then iam changing its state from logic 1 to 0. During this operation the PNP should turn 'ON'. At that instant the o/p current at the port(at 2V during transition)will be 650uA thus forming high apposing current and preventing the PNP to sink its base current.
Is this what that happens?
If so, please tell me how i should work on in my port driver circuit in avoiding (or) to make use of this transition condition.

Erik said:

nice copy of the datasheet, where is the question

Just tried to show what i understood from the datasheet with an example. to make the discussion clear.

Erik said:

WHAT driver circuit, what connection?

I need to get clear with the characteristics of the port pins during i/o operations to design the driver circuit appropriately.

Thanking you all

List of 19 messages in thread
AT89s52 Port pin clarifications:      Suresh R      02/16/06 02:14      
   nice copy, where is the question      Erik Malund      02/16/06 06:30      
   output characteristics      Jan Waclawek      02/16/06 06:53      
      most confusing post      Jez Smith      02/16/06 07:34      
   Answers      Kai Klaas      02/16/06 10:35      
      Logic 1 to 0 transition      Suresh R      02/17/06 05:01      
         You haven't read the 'bible' chapter...      Kai Klaas      02/17/06 08:38      
            no details about transition from logic 1      Suresh R      02/18/06 03:27      
               other way 'round      Jan Waclawek      02/18/06 04:21      
               There ARE!!      Kai Klaas      02/18/06 06:54      
                  pFET2      Suresh R      02/19/06 07:29      
                     Weak and very weak pull-ups      Kai Klaas      02/20/06 07:19      
      maintaining low source impedence?      Suresh R      02/20/06 03:39      
         by making thje driver a sink............      Abhishek Singh      02/21/06 10:02      
         Pull-downs create problems      Kai Klaas      02/22/06 08:00      
            Maximum IOL per port pin: 10 mA ?      Suresh R      02/23/06 04:43      
               IOL      Kai Klaas      02/23/06 06:22      
                  IOL = 10mA or 1.6mA? in port 1      Suresh R      02/23/06 22:26      
                     Depends on load      Kai Klaas      02/25/06 07:40      

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