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Andy Peters
03/06/06 11:49
Read: 419 times
Tucson, Az

#111424 - re: not exactly
Responding to: Richard Erlacher's previous message
Richard Erlacher said:
The BIG thing with CPLD's as opposed to FPGA's is that the timing is quite deterministic and mostly quite independent of which macrocell is used for which function, while FPGA timing can be severely impacted by signal routing delays. That's why it's easier to use the CPLD's.

True. But what always annoyed me about the CPLD fitter tools until recently is that they would tell you how many logic levels your design required, rather than telling you the maximum clock frequency and/or combinatorial delay time. Cripes, the tools are run on a computer; surely, the computer can't do the hard work of mapping logic levels to delays and give me a number? Oy. Yes, Lattice, I'm talkin' 'bout you!

First of all, you can preassign the pinout with very high confidence that it will work out as you plan.

Except in the cases where you're filling the whole chip and you can't route between sections, but if you blow away pinouts it fits fine. Ugh. Having said that, we always do layouts in parallel with CPLD/FPGA logic design, and rarely (but it still happens) do we run into this problem. It was a lot worse in the Old Days of FPGAs where you really had to let the tools choose the pinout.

CPLD's however, have relatively few registers and lots of logic potential. However, in either device type, once you use a register or gate, the entire logic element (or half or quarter element, in some FPGA structures) is used, whether it's an inverter or a tristate flipflop with set/reset and enable.

Not true any more! Modern devices have enough routing resources to let you use the flip-flop independently of the rest of the logic in the macrocell/slice. This is especially true for FPGAs, where there are a lot of flip-flops and sometimes you need wide logic (address decoders, whatever).


List of 21 messages in thread
Atera FPGAs      Mahmood Elnasser      02/25/06 07:03      
   Correction      Mahmood Elnasser      02/25/06 07:30      
      Careful, now ...      Richard Erlacher      03/04/06 11:26      
         modelsim is fine for altera fpgas      Jez Smith      03/04/06 11:38      
            Maybe, but probably not for these parts      Richard Erlacher      03/04/06 11:55      
               you use it seperatly      Jez Smith      03/04/06 12:02      
                  aye, there's the rub ...      Richard Erlacher      03/04/06 12:11      
                     However with altera tools      Jez Smith      03/04/06 15:02      
                        Have you tried that?      Richard Erlacher      03/04/06 15:14      
                           yep just done it now with baseline      Jez Smith      03/04/06 23:54      
                     re: the rub      Andy Peters      03/05/06 22:24      
      Altera EPLDs      Andy Peters      03/05/06 22:28      
         not exactly      Richard Erlacher      03/06/06 00:58      
            re: not exactly      Andy Peters      03/06/06 11:49      
               Maybe you can show me ...      Richard Erlacher      03/07/06 03:36      
                  FPGA thoughts      Andy Peters      03/08/06 10:44      
                     We all have thoughts...      Richard Erlacher      03/09/06 23:29      
   Maxplus or Quartus      Oliver Sedlacek      02/25/06 15:03      
      Do they have free simulation?      Mahmood Elnasser      02/25/06 15:07      
         Programmer      J. Guy      02/28/06 15:06      
         Altera free simulator      Andy Peters      03/05/06 21:58      

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