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Richard Erlacher
03/07/06 03:36
Read: 423 times
Denver, Co

#111489 - Maybe you can show me ...
Responding to: Andy Peters's previous message
You say,

"Not true any more! Modern devices have enough routing resources to let you use the flip-flop independently of the rest of the logic in the macrocell/slice. This is especially true for FPGAs, where there are a lot of flip-flops and sometimes you need wide logic (address decoders, whatever)."

but I have my doubts.

I find the limitations of LUT widths and the added delays associated with concatenating LUT's in order to build a wide gate a real pain. It's a pain in wide comparators, long synchronous counters, and in wide adders. The extra flops would be handy in a carry-save type.

If it's realistic to use the flipflop associated with, say, a Spartan-II LUT in combination with logic in a different logic cell, I'd appreciate a pointer to an app-note or something. Likewise, if you know where Altera makes that possible in their "standard" FPGA families, e.g. 10K, 20K, etc, (you know, the ones you can still get in qfp's) a pointer to that would be appreciated as well.

As for the CPLD's, well, XILINX and Altera make it pretty plain what the delays are, and, of course, they show up in simulation.

The old MACH series devices from AMD and Lattice didn't have such support, and it's too bad. Their product-term sharing scheme was nice but slow, and a couple of passes through that AND the product term array for your local logic block, and you had a 30 ns propagation in a 10 ns part. Of course, their simulation was only "functional."


List of 21 messages in thread
Atera FPGAs      Mahmood Elnasser      02/25/06 07:03      
   Correction      Mahmood Elnasser      02/25/06 07:30      
      Careful, now ...      Richard Erlacher      03/04/06 11:26      
         modelsim is fine for altera fpgas      Jez Smith      03/04/06 11:38      
            Maybe, but probably not for these parts      Richard Erlacher      03/04/06 11:55      
               you use it seperatly      Jez Smith      03/04/06 12:02      
                  aye, there's the rub ...      Richard Erlacher      03/04/06 12:11      
                     However with altera tools      Jez Smith      03/04/06 15:02      
                        Have you tried that?      Richard Erlacher      03/04/06 15:14      
                           yep just done it now with baseline      Jez Smith      03/04/06 23:54      
                     re: the rub      Andy Peters      03/05/06 22:24      
      Altera EPLDs      Andy Peters      03/05/06 22:28      
         not exactly      Richard Erlacher      03/06/06 00:58      
            re: not exactly      Andy Peters      03/06/06 11:49      
               Maybe you can show me ...      Richard Erlacher      03/07/06 03:36      
                  FPGA thoughts      Andy Peters      03/08/06 10:44      
                     We all have thoughts...      Richard Erlacher      03/09/06 23:29      
   Maxplus or Quartus      Oliver Sedlacek      02/25/06 15:03      
      Do they have free simulation?      Mahmood Elnasser      02/25/06 15:07      
         Programmer      J. Guy      02/28/06 15:06      
         Altera free simulator      Andy Peters      03/05/06 21:58      

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