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Andy Peters
03/08/06 10:44
Read: 443 times
Tucson, Az

#111631 - FPGA thoughts
Responding to: Richard Erlacher's previous message
"I find the limitations of LUT widths and the added delays associated with concatenating LUT's in order to build a wide gate a real pain. It's a pain in wide comparators, long synchronous counters, and in wide adders. The extra flops would be handy in a carry-save type."

A handful of points:

a) I do all of my FPGA designs in an HDL (I'm bilingual and speak both Verilog and VHDL, and I've been doing HDLs for over ten years). I'll never go back to schematic entry.

b) as a result of a), I let the synthesis tool do all the heavy lifting. If I want an address decoder, I write a comparator. And I depend on the fact that

c) modern FPGA fabrics are "fast enough" to implement wide decoders and big counters without the floorplanning and hand tweaks that were necessary to get older devices to meet timing, and

d) modern synthesis tools, even the free tools from Brand A and Brand X, are really good at what they do (esp. compared to the absymal tools from ten years ago). The tools really do understand the particular chip resources and will infer RAMs, shift registers and whatever with ease. Of course you have to instantiate black boxes for vendor-specific things like clock PLL/DLLs and you are of course encouraged by the chip vendors to use their IP (FIFOs, DSP blocks, PCI cores, whatever) which also get instantiated as black boxes.

Of course you need to specify completely your timing and area requirements; otherwise the tools will do whatever's quickest.


List of 21 messages in thread
Atera FPGAs      Mahmood Elnasser      02/25/06 07:03      
   Correction      Mahmood Elnasser      02/25/06 07:30      
      Careful, now ...      Richard Erlacher      03/04/06 11:26      
         modelsim is fine for altera fpgas      Jez Smith      03/04/06 11:38      
            Maybe, but probably not for these parts      Richard Erlacher      03/04/06 11:55      
               you use it seperatly      Jez Smith      03/04/06 12:02      
                  aye, there's the rub ...      Richard Erlacher      03/04/06 12:11      
                     However with altera tools      Jez Smith      03/04/06 15:02      
                        Have you tried that?      Richard Erlacher      03/04/06 15:14      
                           yep just done it now with baseline      Jez Smith      03/04/06 23:54      
                     re: the rub      Andy Peters      03/05/06 22:24      
      Altera EPLDs      Andy Peters      03/05/06 22:28      
         not exactly      Richard Erlacher      03/06/06 00:58      
            re: not exactly      Andy Peters      03/06/06 11:49      
               Maybe you can show me ...      Richard Erlacher      03/07/06 03:36      
                  FPGA thoughts      Andy Peters      03/08/06 10:44      
                     We all have thoughts...      Richard Erlacher      03/09/06 23:29      
   Maxplus or Quartus      Oliver Sedlacek      02/25/06 15:03      
      Do they have free simulation?      Mahmood Elnasser      02/25/06 15:07      
         Programmer      J. Guy      02/28/06 15:06      
         Altera free simulator      Andy Peters      03/05/06 21:58      

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