Of course not the bitwise method!

There are algorithms processing a byte "in parallel", derived mostly from the fact that most CRC polys have only a few bits set (this is not a coincidence - in this way, in the hardware implementation, the LFSR has only a few taps - that converts to the number of XORS and that relates directly to the maximum achievable speed and of course also silicon area). It takes then only a couple of xors and shifts to do all the job.

The '51 implementation of such for the CCITT CRC-16 (0x1021) takes me 27 cycles per byte (on the vanilla '51 and those which have the same cycle-per-instruction structure, of course); on AVR it's 38 (here, CRC is kept in memory and to move it in and out is expensive - it would be significantly less if the CRC would be kept in registers).

Can you please look up your old programs and get the figures for the table-driven version, so we are able to compare (a now hastily-written full-table one for '51 came out 19 cycles for me, but maybe you have a better one)?

JW