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Jez Smith
05/19/12 02:29
Read: 501 times
Birmingham
England


 
#187430 - It didnt work because
Responding to: Mahmood Elnasser's previous message
VHDL doesn't allow ports with just outputs, same as it doesn't allow ports with just inputs.
Even with very simple examples its always best to still the code though some kind of simulator, and you can use the synthesis tools to show you how the code has been implemented.VHDL compilers are notorious for producing the most useless error messages in the entire history of the universe so don't rely on them to tell you whats going wrong.

List of 7 messages in thread
TopicAuthorDate
verilog to vhdl      Mahmood Elnasser      05/18/12 00:09      
   Problem solved      Mahmood Elnasser      05/18/12 05:55      
      It didnt work because      Jez Smith      05/19/12 02:29      
         Check out this site      Jez Smith      05/19/12 02:39      
            Verilog      Mahmood Elnasser      05/19/12 03:47      
               Why not?      Jez Smith      05/19/12 04:36      
                  employers!!!      Mahmood Elnasser      05/19/12 05:18      

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