Xilinx use Delay locked loops for their clock multipliers and altera use phase locked loops for theirs, not much difference in performance other than a with a PLL it is possible to have lower jitter on the output than the input, and its not possible on a DLL.
if you look at this datasheet you will see that the CLK0 output is the multiplied clock output with 0 phase shift,so that is usually the output that you use.
the programmable delays are accurate because they are built into the substrate with a mux on the outputs.

http://www.xilinx.com/support/d...module.pdf

you shouldn't edit files generated by the coregen unless you know what you are doing cos you can break them.

Altera and xilinx are about equal in terms of cost and performance, if you really want high resolution timing have a look at these http://www.acam-usa.com/Time-To-D...rters.html
They have one or two strange requirements but I was going to use them for the alien detector for Steve.