Email: Password: Remember Me | Create Account (Free)

Back to Subject List

Old thread has been locked -- no new posts accepted in this thread
Mahmood Elnasser
07/10/12 20:09
Read: 1886 times
Sacramento
USA


 
#187903 - VHDL DCM problem
I'm trying to multiply the frequency of spartan-3e 1600k microblaze dev kit using the DCM core generator with no success.
here is my simple code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity pulsegen is
    Port ( clkin    : in  STD_LOGIC;
           pulseOut : out STD_LOGIC);
end pulsegen;

architecture Behavioral of pulsegen is
	COMPONENT myDCM
	PORT(
		CLKIN_IN : IN std_logic;          
		CLKFX_OUT : OUT std_logic;
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic
		);
	end component;

signal clkfxout, xxx, clk0out, cigo : std_logic;
begin
	Inst_myDCM: myDCM PORT MAP(
		CLKIN_IN => clkin,
		CLKFX_OUT => clkfxout,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => open
	);
	process (clkfxout)
		begin
			if rising_edge(clkfxout) then
				xxx <= (xxx xor '1');
			end if;
		end process;
	pulseOut <= xxx;
end Behavioral;

 

the synthesizer gives me these wanings:
WARNING:Xst:753 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'myDCM'.
WARNING:Xst:753 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Unconnected output port 'CLK0_OUT' of component 'myDCM'.
WARNING:Xst:2211 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Instantiating black box module <myDCM>.
WARNING:Xst:1780 - Signal <clk0out> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <cigo> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
However when I implement the design I get this error message:
ERROR:NgdBuild:604 - logical block 'Inst_myDCM' with type 'myDCM' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'myDCM' is not supported in target
'spartan3e'.
I read the xapp462 which quite nicely describes the DCM but there is no examples how to uses it.
Mahmood

List of 19 messages in thread
TopicAuthorDate
VHDL DCM problem      Mahmood Elnasser      07/10/12 20:09      
   coregen      Maarten Brock      07/11/12 03:04      
      Example found in tool itself!      Mahmood Elnasser      07/11/12 04:48      
         Xilinx DCM      Andy Peters      07/12/12 04:14      
            BUFG      Mahmood Elnasser      07/12/12 09:55      
               re: BUFG      Andy Peters      07/13/12 03:27      
                  Can you share it?      Mahmood Elnasser      07/13/12 04:39      
            Basically don't use coregen      Jez Smith      07/13/12 08:40      
               Altera and Xilinx , probably lattice soon      Mahmood Elnasser      07/13/12 09:27      
                  Altera joy      Jez Smith      07/14/12 08:52      
                  USB blaster clones      Dejan Durdenic      07/14/12 20:59      
   it's working!!!!      Mahmood Elnasser      07/14/12 03:46      
   this warning...      Jez Smith      07/21/12 15:39      
      I don't know      Mahmood Elnasser      07/22/12 09:57      
         new warning      Mahmood Elnasser      07/23/12 09:12      
            contraints      Andy Peters      07/24/12 14:42      
               No change to source      Mahmood Elnasser      07/24/12 23:03      
                  Timing Constraints        Justin Fontes      07/25/12 10:15      
      CoreGen FTL      Andy Peters      07/24/12 14:41      

Back to Subject List