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Andy Peters
07/12/12 04:14
Read: 806 times
Tucson, Az

#187914 - Xilinx DCM
Responding to: Mahmood Elnasser's previous message
Mahmood Elnasser said:
Maarten Brock said:
Try to setup the DCM with the core generator.

That's what I did. The core generator is to make things simple.
Anyway I found an example in the ISE14.1 itself that uses the DCM which I'm deciphering now. File -> open example -> stopwatch vhd for xc3s100. It has exactly what I'm looking for.
I don't know why I learn from examples better than reading 10 books!
Thanks Maarten

After doing Xilinx for a million years, I no longer use the Core Generator. But for setting up DCMs, it actually helps. Of course, now I have a template, and I tend to put an entity called clocks.vhdl in all of my designs; that entity is where all clocks are derived and it neatly wraps up the DCMs and the associated buffers.

The important thing to remember is that XST is really kinda stupid, and you have to instantiate the BUFGs for all of the DCM inputs and outputs.

So, at minimum, you need a BUFG for the input clock (which drives the DCM CLKIN) and a BUFG for each output. So if you use CLK0, CLK2X and CLKFX, you need three more BUFGs. In addition, the output of the CLK0 BUFG should be used to drive the CLKFB input (and set the generic that indicates clock feedback 1X or 2X to 1X).

And it gets worse: ISE is too stupid to correctly place the location of the buffers. You'll get a dire warning about how the BUFGMUX (which is really what you get when you instantiate a BUFG) is placed on the other side of the FPGA, precluding using the fast clock path from the clock input pin. Yes, the tools put the BUFGMUX on the wrong side of the chip, even though the documentation makes quite clear which BUFGMUX is associated with which GCLK input pin and which DCM. So, at minimum, you'll have to LOC the BUFGMUX connected to the input pin.

Good luck!


List of 19 messages in thread
VHDL DCM problem      Mahmood Elnasser      07/10/12 20:09      
   coregen      Maarten Brock      07/11/12 03:04      
      Example found in tool itself!      Mahmood Elnasser      07/11/12 04:48      
         Xilinx DCM      Andy Peters      07/12/12 04:14      
            BUFG      Mahmood Elnasser      07/12/12 09:55      
               re: BUFG      Andy Peters      07/13/12 03:27      
                  Can you share it?      Mahmood Elnasser      07/13/12 04:39      
            Basically don't use coregen      Jez Smith      07/13/12 08:40      
               Altera and Xilinx , probably lattice soon      Mahmood Elnasser      07/13/12 09:27      
                  Altera joy      Jez Smith      07/14/12 08:52      
                  USB blaster clones      Dejan Durdenic      07/14/12 20:59      
   it's working!!!!      Mahmood Elnasser      07/14/12 03:46      
   this warning...      Jez Smith      07/21/12 15:39      
      I don't know      Mahmood Elnasser      07/22/12 09:57      
         new warning      Mahmood Elnasser      07/23/12 09:12      
            contraints      Andy Peters      07/24/12 14:42      
               No change to source      Mahmood Elnasser      07/24/12 23:03      
                  Timing Constraints        Justin Fontes      07/25/12 10:15      
      CoreGen FTL      Andy Peters      07/24/12 14:41      

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