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Mahmood Elnasser
07/24/12 23:03
Read: 483 times
Sacramento
USA


 
#187972 - No change to source
Responding to: Andy Peters's previous message
Andy Peters said:
Did you make any changes in the source between runs?
-a

No and yes I always add timing constraints.
The DCM core gen is very attractive for beginners because it is so easy to use, just fill the form and it generates the code for you. Have you tried it?
Mahmood


List of 19 messages in thread
TopicAuthorDate
VHDL DCM problem      Mahmood Elnasser      07/10/12 20:09      
   coregen      Maarten Brock      07/11/12 03:04      
      Example found in tool itself!      Mahmood Elnasser      07/11/12 04:48      
         Xilinx DCM      Andy Peters      07/12/12 04:14      
            BUFG      Mahmood Elnasser      07/12/12 09:55      
               re: BUFG      Andy Peters      07/13/12 03:27      
                  Can you share it?      Mahmood Elnasser      07/13/12 04:39      
            Basically don't use coregen      Jez Smith      07/13/12 08:40      
               Altera and Xilinx , probably lattice soon      Mahmood Elnasser      07/13/12 09:27      
                  Altera joy      Jez Smith      07/14/12 08:52      
                  USB blaster clones      Dejan Durdenic      07/14/12 20:59      
   it's working!!!!      Mahmood Elnasser      07/14/12 03:46      
   this warning...      Jez Smith      07/21/12 15:39      
      I don't know      Mahmood Elnasser      07/22/12 09:57      
         new warning      Mahmood Elnasser      07/23/12 09:12      
            contraints      Andy Peters      07/24/12 14:42      
               No change to source      Mahmood Elnasser      07/24/12 23:03      
                  Timing Constraints        Justin Fontes      07/25/12 10:15      
      CoreGen FTL      Andy Peters      07/24/12 14:41      

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