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Richard Erlacher
01/31/16 14:19
Modified:
  01/31/16 14:22

Read: 421 times
Denver, Co
USA


 
#190613 - one other thing ...
Responding to: Mehdi's previous message
With AC logic, the propogation delays are generally specified with a significant capacitive load, as that's what they often drive. If you build a simple circuit with little capacitive loading, you'll find the prop-delays are closer to the specified minima, rather than the 40 or 50 pf load they specify. Look at the datasheets from Fairchild, for example. The prop-delay I've seen on a 74AC86 has been closer 3 ns in my obervation, rather than the maximum shown in the sheet. Further, the clock-to-Q for the AC74 is close to 4 ns. I don't recall whether I mentioned that the output of that circuit is the output of the XOR. The first transition, BTW, may be different from the rest of them, but each one after that should reflect only the Clock-to-Q of the 'AC74, as the delay in the XOR remains a constant.

If I feed a 1 kHz square wave to that xor clocking DFF I described, you get a very nearly 5 ns pulse every half-millisecond. That circuit, BTW, is an edge detector, not a fequency doubler, as it reflects the input signal's duty cycle. It simply produces a positive transition for each transition of the input signal.

RE

List of 7 messages in thread
TopicAuthorDate
making a Glitch?      MEHDI      11/20/15 12:38      
   Search for |Avalanche diode pulse generator      Mahmood Elnasser      11/22/15 09:24      
      Thanks      MEHDI      11/23/15 08:05      
      you might be able to do it with logic      Richard Erlacher      11/26/15 00:08      
         Thanks      MEHDI      12/30/15 06:51      
            you might be able to do that ...       Richard Erlacher      01/14/16 18:01      
            one other thing ...       Richard Erlacher      01/31/16 14:19      

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