/*-------------------------------------------------------------------------
REG66x.H

Archivo Header para microcontoladores Philips 8xC660/662/664
  
Copyright (c) 2005 Omar Espinosa. e-mail: opiedrahita2003@yahoo.com
--------------------------------------------------------------------------*/

#ifndef __REG66x_H__
#define __REG66x_H__

sfr  P0          0x80;			 

sbit at   0x87        P0_7;
sbit at   0x86        P0_6;
sbit at   0x85        P0_5;
sbit at   0x84        P0_4;
sbit at   0x83        P0_3;
sbit at   0x82        P0_2;
sbit at   0x81        P0_1;
sbit at   0x80        P0_0;


#define  AD6        P0_6 
#define  AD5        P0_5 
#define  AD4        P0_4 
#define  AD3        P0_3 
#define  AD2        P0_2 
#define  AD1        P0_1 
#define  AD0        P0_0 


sfr  SP          0x81;
sfr  DPL         0x82;
sfr  DPH         0x83;

sfr  PCON        0x87;			 

sfr  TCON        0x88;             

sbit at    0x8F        TCON_7 
sbit at    0x8E        TCON_6 
sbit at    0x8D        TCON_5 
sbit at    0x8C        TCON_4 
sbit at    0x8B        TCON_3 
sbit at    0x8A        TCON_2 
sbit at    0x89        TCON_1 
sbit at    0x88        TCON_0 

sbit at   TF1        TCON_7 
sbit at   TR1        TCON_6 
sbit at   TF0        TCON_5 
sbit at   TR0        TCON_4 
sbit at   IE1_       TCON_3 
sbit at   IT1        TCON_2 
sbit at   IE0_       TCON_1 
sbit at   IT0        TCON_0 


sfr  TMOD        0x89;			 

sfr  TL0         0x8A;			 

sfr  TL1         0x8B;			 

sfr  TH0         0x8C;			 

sfr  TH1         0x8D;			 

sfr  P1          0x90;			 

sbit  SDA         P1_7;
sbit  SCL         P1_6;
sbit  CEX2        P1_5;
sbit  CEX1        P1_4;
sbit  CEX0        P1_3;
sbit  ECI         P1_2;
sbit  T2EX        P1_1;
sbit  T2          P1_0;

sfr  S0CON        0x98;			 
sfr  S1CON     	  0xD8;

sbit  SM0        S0CON_7;
sbit  FE         S0CON_7;
sbit  SM1        S0CON_6;
sbit  SM2        S0CON_5;
sbit  REN        S0CON_4;
sbit  TB8        S0CON_3;
sbit  RB8        S0CON_2;
sbit  TI         S0CON_1;
sbit  RI         S0CON_0;

sbit  CR2        S1CON_7;
sbit  ENS1       S1CON_6;
sbit  STA        S1CON_5;
sbit  STO        S1CON_4;
sbit  SI         S1CON_3;
sbit  AA         S1CON_2;
sbit  CR1        S1CON_1;
sbit  CR0        S1CON_0;

sfr  S0BUF        0x99;			 

sfr  P2          0xA0;			 

sbit  AD15        P2_7;
sbit  AD14        P2_6;
sbit  AD13        P2_5;
sbit  AD12        P2_4;
sbit  AD11        P2_3;
sbit  AD10        P2_2;
sbit  AD9         P2_1;
sbit  AD8         P2_0;

sfr  IEN0        0xA8;

sbit  EA         IEN0_7;
sbit  EC         IEN0_6;
sbit  ES1        IEN0_5;
sbit  ES0        IEN0_4;
sbit  ET1        IEN0_3;
sbit  EX1        IEN0_2;
sbit  ET0        IEN0_1;
sbit  EX0        IEN0_0;

sfr IEN1	  0xE8;

sbit  ET2        IEN1_0;


sfr  SADDR       0xA9;			 

sfr  P3          0xB0;			 

sbit  RD          P3_7;
sbit  WR          P3_6;
sbit  T1          P3_5;
sbit  T0          P3_4;
sbit  INT1        P3_3;
sbit  INT0        P3_2;
sbit  TXD         P3_1;
sbit  RXD         P3_0;

sfr  IPH          0xB7;			     
sfr  IP           0xB8;


sfr  SADEN       0xB9;			 
	

sbit  PT2          IP_7;
sbit  PPC          IP_6;
sbit  PS1          IP_5;
sbit  PS0          IP_4;
sbit  PT1          IP_3;
sbit  PX1          IP_2;
sbit  PT0          IP_1;
sbit  PX0          IP_0;

sfr  T2CON       0xC8;             

sbit  TF2        T2CON_7;
sbit  EXF2       T2CON_6;
sbit  RCLK       T2CON_5;
sbit  TCLK       T2CON_4;
sbit  EXEN2      T2CON_3;
sbit  TR2        T2CON_2;
sbit  CT2        T2CON_1;
sbit  CP         T2CON_0;

sfr  T2MOD       0xC9;			 

sfr  RCAP2L      0xCA;			 
sfr  RCAP2H      0xCB;			 
sfr  TL2         0xCC;			 
sfr  TH2         0xCD;			 

sfr  PSW         0xD0;			 
sbit  CY         PSW_7;
sbit  AC         PSW_6;
sbit  F0         PSW_5;
sbit  RS1        PSW_4;
sbit  RS0        PSW_3;
sbit  OV         PSW_2;
sbit  UD         PSW_1;
sbit  P          PSW_0;

			 
sfr  ACC         0xE0;			 
sfr  B           0xF0;			 

sfr  CCON        0xC0;	
sbit  CF         CCON_7;
sbit  CR         CCON_6;
sbit  CCF4       CCON_4;
sbit  CCF3       CCON_3;
sbit  CCF2       CCON_2;
sbit  CCF1       CCON_1;
sbit  CCF0       CCON_0;		 

sfr  CMOD        0xC1;			 
sfr  CCAPM0      0xC2;			 
sfr  CCAPM1      0xC3;			 
sfr  CCAPM2      0xC4;			 
sfr  CCAPM3      0xC5;			 
sfr  CCAPM4      0xC6;	

sfr  CL          0xE9;			 
sfr  CCAP0L      0xEA;			 
sfr  CCAP1L      0xEB;			 
sfr  CCAP2L      0xEC;			 
sfr  CCAP3L      0xED;			 
sfr  CCAP4L      0xEE;			 

sfr  CH          0xF9;			 
sfr  CCAP0H      0xFA;			 
sfr  CCAP1H      0xFB;			  
sfr  CCAP2H      0xFC;			 
sfr  CCAP3H      0xFD;			 
sfr  CCAP4H      0xFE;	



sfr AUXR	  0x8E;
sfr AUXR1	  0xA2;

sfr     S1DAT	        0xDA;
sfr	S1IST	 	0xDC;
sfr	S1ADR	 	0xDB;
sfr	S1STA	 	0xD9;

sfr     WDTRST         0xA6;
#endif