//------------------------------------------------------------------//--------
//REG922.H

//Header file for Philips 89LPC920 / 89LPC921 / 89LPC922
//Copyright (c) 2005 Omar de Jesus Espinosa P. opiedrahita2003@yahoo.com
//All rights reserved.
//V1.0
//------------------------------------------------------------------//--//------*/
#ifndef __922sdcc_H__
#define __REG922_H__
#define __REG922_H__

//*  BYTE Registers  *//
sfr at 0x80 P0     ;
sfr at 0x90 P1     ;
sfr at 0xB0 P3     ;
sfr at 0xD0 PSW    ;
sfr at 0xE0 ACC    ;
sfr at 0xF0 B      ;
sfr at 0x81 SP     ;
sfr at 0x82 DPL    ;
sfr at 0x83 DPH    ;
sfr at 0x87 PCON   ;
sfr at 0x88 TCON   ;
sfr at 0x89 TMOD   ;
sfr at 0x8A TL0    ;
sfr at 0x8B TL1    ;
sfr at 0x8B TH0    ;
sfr at 0x8D TH1    ;
sfr at 0xA8 IEN0   ;
sfr at 0xB8 IP0    ;
sfr at 0x98 SCON   ;
sfr at 0x99 SBUF   ;


sfr at 0xA2 AUXR1  ;
sfr at 0xA9 SADDR  ;
sfr at 0xB9 SADEN  ;
sfr at 0xBE BRGR0  ;
sfr at 0xBF BRGR1  ;
sfr at 0xBD BRGCON ;
sfr at 0xAC CMP1   ;
sfr at 0xAD CMP2   ;
sfr at 0x95 DIVM   ;
sfr at 0xE7 FMADRH ;
sfr at 0xE6 FMADRL ;
sfr at 0xE4 FMCON  ;
sfr at 0xE5 FMDATA ;
sfr at 0xDB I2ADR  ;
sfr at 0xD8 I2CON  ;
sfr at 0xDA I2DAT  ;
sfr at 0xDD I2SCLH ;
sfr at 0xDC I2SCLL ;
sfr at 0xD9 I2STAT ;
sfr at 0xF8 IP1    ;
sfr at 0xF7 IP1H   ;
sfr at 0x94 KBCON  ;
sfr at 0x86 KBMASK ;
sfr at 0x93 KBPATN ;
sfr at 0x84 P0M1   ;
sfr at 0x85 P0M2   ;
sfr at 0x91 P1M1   ;
sfr at 0x92 P1M2   ;
sfr at 0xB1 P3M1   ;
sfr at 0xB2 P3M2   ;
sfr at 0xB5 PCONA  ;
sfr at 0xF6 PT0AD  ;
sfr at 0xDF RSTSRC ;
sfr at 0xD1 RTCCON ;
sfr at 0xD2 RTCH   ;
sfr at 0xD3 RTCL   ;
sfr at 0xBA SSTAT  ;
sfr at 0x8F TAMOD  ;
sfr at 0x96 TRIM   ;
sfr at 0xA7 WDCON  ;
sfr at 0xC1 WDL    ;
sfr at 0xC2 WFEED1 ;
sfr at 0xC3 WFEED2 ;
sfr at 0xB7 IP0H   ;
sfr at 0xE8 IEN1   ;

/*  BIT Registers  */
/*  PSW   */
#define CY  PSW_7
#define AC  PSW_6
#define F0  PSW_5
#define RS1 PSW_4
#define RS0 PSW_3
#define OV  PSW_2
#define F1  PSW_1
#define P   PSW_0

sbit at 0xD0 PSW_0   ;
sbit at 0xD1 PSW_1   ;
sbit at 0xD2 PSW_2   ;
sbit at 0xD3 PSW_3   ;
sbit at 0xD4 PSW_4   ;
sbit at 0xD5 PSW_5   ;
sbit at 0xD6 PSW_6   ;
sbit at 0xD7 PSW_7   ; 

/*  TCON  */
sbit at 0x8F TCON_7  ;
sbit at 0x8E TCON_6  ;
sbit at 0x8D TCON_5  ;
sbit at 0x8C TCON_4  ;
sbit at 0x8B TCON_3  ;
sbit at 0x8A TCON_2  ;
sbit at 0x89 TCON_1  ;
sbit at 0x88 TCON_0  ;

#define TF1 TCON_7 
#define TR1 TCON_6 
#define TF0 TCON_5 
#define TR0 TCON_4 
#define IE1 TCON_3 
#define IT1 TCON_2 
#define IE0 TCON_1 
#define IT0 TCON_0 

/*  IEN0   */
#define EA IEN0_7 
#define EWDRT IEN0_6 
#define EBO IEN0_5 
#define ES IEN0_4    // alternatively "ESR"
#define ESR IEN0_4  
#define ET1 IEN0_3 
#define EX1 IEN0_2 
#define ET0 IEN0_1
#define EX0 IEN0_0



sbit at 0xAF IEN0_7 ;
sbit at 0xAE IEN0_6 ;
sbit at 0xAD IEN0_5 ;
sbit at 0xAC IEN0_4 ; 
sbit at 0xAB IEN0_3 ;
sbit at 0xAA IEN0_2 ;
sbit at 0xA9 IEN0_1 ;
sbit at 0xA8 IEN0_0 ;

/*  IEN1   */
sbit at 0xEA IEN1_2 ;
sbit at 0xE9 IEN1_1 ;
sbit at 0xE8 IEN1_0 ;

#define EC   IEN1_2 
#define EKBI IEN1_1 
#define EI2C IEN1_0 

/*  IP1   */ 
#define PST  IP1_6 
#define PC   IP1_2 
#define PKBI IP1_1 
#define PI2C IP1_0 

sbit at 0xFE IP1_6 ;
sbit at 0xFA IP1_2 ;
sbit at 0xF9 IP1_1 ;
sbit at 0xF8 IP1_0 ;

/*  IP0   */ 
sbit at 0xBE IP0_6 ;
sbit at 0xBD IP0_5 ;
sbit at 0xBC IP0_4 ; // alternatively "PSR"
sbit at 0xBB IP0_3 ;
sbit at 0xBA IP0_2 ;
sbit at 0xB9 IP0_1 ;
sbit at 0xB8 IP0_0 ;

#define PWDRT IP0_6 
#define PBO   IP0_5 
#define PS    IP0_4      // alternatively "PSR"
#define PSR   IP0_4 
#define PT1   IP0_3 
#define PX1   IP0_2 
#define PT0   IP0_1 
#define PX0   IP0_0 


/*  SCON  */
#define SM0  SCON_7  // alternatively "FE"
#define FE   SCON_7
#define SM1  SCON_6
#define SM2  SCON_5
#define REN  SCON_4
#define TB8  SCON_3
#define RB8  SCON_2
#define TI   SCON_1
#define RI   SCON_0

sbit at 0x98 SCON_0   ;
sbit at 0x99 SCON_1   ;
sbit at 0x9A SCON_2   ;
sbit at 0x9B SCON_3   ;
sbit at 0x9C SCON_4   ;
sbit at 0x9D SCON_5   ;
sbit at 0x9E SCON_6   ;
sbit at 0x9F SCON_7   ;
             
/*  I2CON  */
#define I2EN   I2CON_6
#define STA    I2CON_5
#define STO    I2CON_4
#define SI     I2CON_3
#define AA     I2CON_2
#define CRSEL  I2CON_0

sbit at 0xDE I2CON_6  ;
sbit at 0xDD I2CON_5  ;
sbit at 0xDC I2CON_4  ;
sbit at 0xDB I2CON_3  ;
sbit at 0xDA I2CON_2  ;
sbit at 0xD8 I2CON_0  ;


/*  P0  */
#define	KB7  P0_7    // alternatively "T1"
#define T1   P0_7
#define KB6  P0_6   // alternatively "CMP1"
#define CMP1 P0_6
#define KB5  P0_5
#define KB4  P0_4
#define KB3  P0_3
#define KB2  P0_2
#define KB1  P0_1
#define KB0  P0_0   // alternatively "CMP2"
#define CMP2 P0_0

/*  P0    */
sbit at 0x80 P0_0 ;
sbit at 0x81 P0_1 ;
sbit at 0x82 P0_2 ;
sbit at 0x83 P0_3 ;
sbit at 0x84 P0_4 ;
sbit at 0x85 P0_5 ;
sbit at 0x86 P0_6 ;
sbit at 0x87 P0_7 ;

/*  P1  */
#define RST  P1_5
#define INT1 P1_4
#define INT0 P1_3	 // alternatively "SDA"
#define SDA  P1_3
#define T0   P1_2       // alternatively "SCL"
#define SCL  P1_2
#define RxD  P1_1
#define TxD  P1_0

sbit at 0x90 P1_0 ; 
sbit at 0x91 P1_1 ;
sbit at 0x92 P1_2 ;
sbit at 0x93 P1_3 ;
sbit at 0x94 P1_4 ;
sbit at 0x95 P1_5 ;

/*  P3  */
#define XTAL1 P3_1
#define XTAL2 P3_0

sbit at 0xB0  P3_0  ;
sbit at 0xB1  P3_1  ;

#endif