Richard's Miscellaneous Hardware Bits Not everyone has seen the sort of WireWrap board I like. I had a number of these made up for use with a proprietary system architecture that I used for many things back in the '70's and '80's. I also had other similar boards made for other architectures, but these are some that I still use, mainly because I still have some of them. I like the size and the fact that nearly everything is easy. It's quite easy to keep power-to-gnd noise below 50 mV on these boards because of the excellent accomodation of supply bypass and low-impedance ground and power planes. Have a look. This board has a dry-film solder mask that makes it easy to avoid contact with the Vcc plane on the component side and with the GND plane on the wiring side of the board. Further, this mask is easily removed in a small region with a little pressure from a sharp instrument because the mask is quite brittle. That makes it easy to bypass supply connections by soldering a cap to the supply pin and soldering the other side of it to the supply plane. It also easily accomodates nearly any popular through-hole socket and ribbon-cable connectors to facilitate communication with other sub- systems inside or outside the enclosure. The strip around the outside of the board on three sides is connected to the ground plane. That way it's easy to attach 'scope ground straps, or ground connections to other test instruments. One question that comes up time and again, despite the fact that the LSI is no longer popular or widely available in many parts of the world, is How to attach an 8255 to a standard 805x? Here's an illustration of ONE way to do it, provided you've already implemented the external data and address busses. As always, it's important that a user be very aware of the timing of the external memory bus, and of the timing requirements of the external devices to be attached via that bus. There are other ways of accomplishing the attachment of an 8255 to an 805x, particularly if one is not willing to provide the external memory bus. This is a way in which it can be done when no external memory bus already exists. This approach demands that the user ensure that the nCS, nWR, and nRD strobes are timed appropriately, and that data is appropriately set up before and held after the nWR strobe. In this case, almost all the bits from two ports are consumed by this interface, which yields, at most, three ports. However, addition of another 8255 which will provide another three ports requires only one additional nCS bit. The remaining signals can be wired in parallel. Of course, the user must manage the duration of the directly generated strobes in firmware, ensuring that they are sufficiently long to permit proper function of the 8255. With this arrangement, it is possible to use even the slowest versions of the 8255, as firmware can adjust the strobe durations. Now, here's a way to interface dynamic memories of at least 64 kbit-depth and 8-bit width. It doesn't matter whether these are in form of DIP's SIPP's, SIMMS, ZIPs, or whatever. The data width is irrelevant. Devices with nOE should probably be enabled on the coincidence (negative logic AND, 74xx32) of nRD and nCAS). Depending on the performance of the DRAMs, this scheme can probably be used with MCU clocks up to 25 MHz. Of course, your mileage may vary. The critical details include (1) setup time of addresses before nRAS and nCAS falling edges is typically 0 ns. It must NEVER be less than that! (2) nWE must occur before nCAS in order to ensure that the cycle is an "early write" which suppresses data output. (3) The cycle time is typically twice the access time, thereby allowing for a "nRAS recovery time" during which all cells in the currently addressed row are refreshed. (4) Each row must be accessed via a nRAS cycle at least once in each refresh cycle. Early DRAMs required that the full cycle be completed each 2 ms. Check your device spec's to ensure the cycle is sufficiently short. One note just to compensate for perhaps poorly chosen nomenclature. There are RAS-only refresh cycles, and there's the entire "refresh cycle." The latter is the period required to complete a full count of, in this case, 256 column addresses. The former is a brief read-cycle-length cycle without nCAS or nWE in order to refresh a row of 256 data bits. The maximal "refresh cycle" is specified by the manufacturer and the refresh counter must be cycled fully within that time and for the specified number of rows. In this case, only 64KB of data are used, so, despite the fact that the device might be a 4MB SIMM, only 8 addresses need be applied and only 256 rows need be refreshed. Aside from power consumption, and the resulting thermal issues, refreshing too often has no adverse effect. It is not unheard-of for a DRAM subsystem to refresh at the maximal rate. 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