-- ***************************************************************** -- *** TRISCEND E5 CONFIGURABLE SYSTEM-ON-CHIP (CSoC) BUS SOCKET *** -- *** (c) 2001 by Triscend Corporation. All Rights Reserved *** -- ***************************************************************** -- -- REVISION HISTORY -- ================ -- 0.01 Initial version by Steve Knapp (sknapp@triscend.com) -- -- 0.02 Modified the way that SFRs Selectors are created. Version 0.01 -- incorrectly used a SELECTSFR primitive instead of a SELECTRANGE -- with an ALLOCATESFR attached to the PHYSICAL port. -- -- 0.03 Added all ports on SELECTRANGE components as per the simulation -- model. library ieee; use ieee.std_logic_1164.all; -- For simulation purposes only -- library triscend; -- use triscend.tcomponents.all; entity e5_csi_socket is generic ( isAutoWaited : boolean := false; -- isAutoWaited = true, then Selector asserts initial wait-state isExternal : boolean := false; -- isExternal = true, then Selector turns on MIU access through MIU isSFR : boolean := false; -- isSFR = true, then allocate the Selector to SFR space decode_pwr2 : positive := 0 -- by default, allocate a single byte ); port ( CSI_A : out std_logic_vector(15 downto 0); CSI_DW : out std_logic_vector(7 downto 0); CSI_DR : in std_logic_vector(7 downto 0); CSI_SYMBOLIC : in std_logic; CSI_WRSEL : out std_logic; CSI_RDSEL : inout std_logic; CSI_WAITED : out std_logic; CSI_EVENT : out std_logic; CSI_WAITNEXT : in std_logic; CSI_BREAK : in std_logic; CSI_BUSCLK : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end e5_csi_socket; architecture structural of e5_csi_socket is signal AutoWait : std_logic := '0'; signal External : std_logic := '0'; signal size : std_logic_vector (31 downto 0); signal addr_alloc : std_logic_vector (31 downto 0); attribute syn_black_box:boolean; type SizeArrayType is array (0 to 16) of std_logic_vector(31 downto 0); constant SizeArray : SizeArrayType := (0 => (X"00000001"), 1 => (X"00000002"), 2 => (X"00000004"), 3 => (X"00000008"), 4 => (X"00000010"), 5 => (X"00000020"), 6 => (X"00000040"), 7 => (X"00000080"), 8 => (X"00000100"), 9 => (X"00000200"), 10 => (X"00000400"), 11 => (X"00000800"), 12 => (X"00001000"), 13 => (X"00002000"), 14 => (X"00004000"), 15 => (X"00008000"), 16 => (X"00010000")); component BUSCLK port ( O : out std_logic; SIM : inout std_logic_vector (127 downto 0) ); end component; attribute syn_black_box of BUSCLK:component is true; component A15_12 port ( A15 : out std_logic; A14 : out std_logic; A13 : out std_logic; A12 : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of A15_12:component is true; component A11_8 port ( A11 : out std_logic; A10 : out std_logic; A9 : out std_logic; A8 : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of A11_8:component is true; component A7_4 port ( A7 : out std_logic; A6 : out std_logic; A5 : out std_logic; A4 : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of A7_4:component is true; component A3_0 port ( A3 : out std_logic; A2 : out std_logic; A1 : out std_logic; A0 : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of A3_0:component is true; component SELECTRANGE port ( SYMBOLIC : in std_logic; PHYSICAL : in std_logic_vector(31 downto 0); SIZE : in std_logic_vector(31 downto 0); LANE : in std_logic_vector(3 downto 0); AWAIT : in std_logic; ORRW : in std_logic; XMEM : in std_logic; SIM : inout std_logic_vector(127 downto 0); RDSEL : out std_logic; WRSEL : out std_logic ); end component; attribute syn_black_box of SELECTRANGE:component is true; component DW7_0 port ( DW7 : out std_logic; DW6 : out std_logic; DW5 : out std_logic; DW4 : out std_logic; DW3 : out std_logic; DW2 : out std_logic; DW1 : out std_logic; DW0 : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of DW7_0:component is true; component DR7_0E port ( DR7 : in std_logic; DR6 : in std_logic; DR5 : in std_logic; DR4 : in std_logic; DR3 : in std_logic; DR2 : in std_logic; DR1 : in std_logic; DR0 : in std_logic; EN : in std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of DR7_0E:component is true; component WTEVT port ( O : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of WTEVT : component is true; component WTCTL port ( I : in std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of WTCTL : component is true; component BPEVT port ( O : out std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of BPEVT : component is true; component BPCTL port ( I : in std_logic; SIM : inout std_logic_vector(127 downto 0) ); end component; attribute syn_black_box of BPCTL : component is true; component ALLOCATE port ( O : OUT std_logic_vector(31 downto 0) ); end component; attribute syn_black_box of ALLOCATE : component is true; component ALLOCATESFR port ( O : OUT std_logic_vector(31 downto 0) ); end component; attribute syn_black_box of ALLOCATESFR : component is true; begin GEN_SIZE: if (true) generate size <= SizeArray(decode_pwr2); end generate; -- If isAutoWaited = true GEN_AUTOWAITED: if (isAutoWaited) generate AutoWait <= '1'; end generate; -- If isExternal = true GEN_EXTERNAL: if (isExternal) generate External <= '1'; end generate; BUSCLK : BUSCLK port map ( O => CSI_BUSCLK, SIM => SIM ); CSI_A15_12 : A15_12 port map ( A15 => CSI_A(15), A14 => CSI_A(14), A13 => CSI_A(13), A12 => CSI_A(12), SIM => SIM ); CSI_A11_8 : A11_8 port map ( A11 => CSI_A(11), A10 => CSI_A(10), A9 => CSI_A(9), A8 => CSI_A(8), SIM => SIM ); CSI_A7_4 : A7_4 port map ( A7 => CSI_A(7), A6 => CSI_A(6), A5 => CSI_A(5), A4 => CSI_A(4), SIM => SIM ); CSI_A3_0 : A3_0 port map ( A3 => CSI_A(3), A2 => CSI_A(2), A1 => CSI_A(1), A0 => CSI_A(0), SIM => SIM ); CSI_DW7_0 : DW7_0 port map ( DW7 => CSI_DW(7), DW6 => CSI_DW(6), DW5 => CSI_DW(5), DW4 => CSI_DW(4), DW3 => CSI_DW(3), DW2 => CSI_DW(2), DW1 => CSI_DW(1), DW0 => CSI_DW(0), SIM => SIM ); CSI_DR7_0 : DR7_0E port map ( DR7 => CSI_DR(7), DR6 => CSI_DR(6), DR5 => CSI_DR(5), DR4 => CSI_DR(4), DR3 => CSI_DR(3), DR2 => CSI_DR(2), DR1 => CSI_DR(1), DR0 => CSI_DR(0), EN => CSI_RDSEL, SIM => SIM ); WAITED : WTEVT port map ( O => CSI_WAITED, SIM => SIM ); WAITNEXT : WTCTL port map ( I => CSI_WAITNEXT, SIM => SIM ); EVENT : BPEVT port map ( O => CSI_EVENT, SIM => SIM ); BREAK : BPCTL port map ( I => CSI_BREAK, SIM => SIM ); SELECTOR: SELECTRANGE port map ( SYMBOLIC => CSI_SYMBOLIC, PHYSICAL => addr_alloc, SIZE => size, LANE => X"0", AWAIT => AutoWait, ORRW => '0', XMEM => External, SIM => SIM, RDSEL => CSI_RDSEL, WRSEL => CSI_WRSEL ); SFR_SPACE: if (isSFR) generate begin ALLOCATE_SFR : ALLOCATESFR port map ( O => addr_alloc ); end generate; XDATA_SPACE: if (not(isSFR)) generate begin ALLOCATE_XDATA : ALLOCATE port map ( O => addr_alloc ); end generate; end structural;