library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity rw_counter is
	port (COUNTER_SYMBOLIC_ADDRESS : in    std_logic;
	      COUNT    : inout std_logic_vector(7 downto 0);
              RDSEL    : inout std_logic;
	      WRSEL    : inout std_logic;
	      RESET    : in    std_logic;
              CSIBUS   : inout std_logic_vector(127 downto 0)
             );
end rw_counter;

architecture structural of rw_counter is

signal D : std_logic_vector(7 downto 0);
signal CLK : std_logic;
signal NC1, NC2 : std_logic;
signal NC3 : std_logic_vector(15 downto 0);
component e5_csi_socket is

    generic ( isAutoWaited : boolean := false; -- isAutoWaited = true, then Selector asserts initial wait-state
	      isExternal   : boolean := false; -- isExternal = true, then Selector turns on MIU access through MIU
              isSFR        : boolean := false; -- isSFR = true, the Selector exports locations for 8051 SFR space 
              decode_pwr2  : positive := 0     -- Specifies number of bytes decoded, size = 2**decode_pwr2
	        );   

    port ( CSI_A : out std_logic_vector(15 downto 0);
	       CSI_DW : out std_logic_vector(7 downto 0);
               CSI_DR : in std_logic_vector(7 downto 0);
	       CSI_SYMBOLIC : in std_logic;
	       CSI_WRSEL : out std_logic;
	       CSI_RDSEL : inout std_logic;
	       CSI_WAITED : out std_logic;
	       CSI_EVENT  : out std_logic;
               CSI_WAITNEXT : in std_logic;
	       CSI_BREAK  : in std_logic;
               CSI_BUSCLK : out std_logic;
	       SIM    : inout std_logic_vector(127 downto 0)
         );

end component;



begin


    CSI_SOCKET: e5_csi_socket
        generic map (
             isAutoWaited  => false, -- zero wait-state
             isSFR         => true,  -- place counter in the 8051's SFR region
             decode_pwr2   => 2      -- set decoder to respond to a 4-byte region, 2**2
	)
        port map (
             CSI_A        => NC3,
             CSI_SYMBOLIC => COUNTER_SYMBOLIC_ADDRESS,
             CSI_DW       => D,
             CSI_DR       => COUNT,
             CSI_WRSEL    => WRSEL,
             CSI_RDSEL    => RDSEL,
             CSI_WAITED   => NC1,
             CSI_EVENT    => NC2,
             CSI_BREAK    => '0',
             CSI_WAITNEXT => '0',
             CSI_BUSCLK   => CLK,
             SIM          => CSIBUS
	);


	COUNTER:  process (CLK, RESET, WRSEL)
	    begin
                if (RESET = '1') then
                    COUNT <= "00000011";  -- reload counter with 0x3 when reset or power-up
		elsif (rising_edge(CLK)) then
            	    if (WRSEL = '1') then
                        COUNT <= D;
                    else
                        COUNT <= COUNT + 1;
                    end if;
                end if;
	end process;

end structural;